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Intel SoC FPGA Embedded Development Suite
Latest Release: v20.3
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PLEASE NOTE: This version of Intel SoC FPGA Embedded Development Suite Software ("Software") does not contain the latest functional and security updates. In order to use this version, you must first acknowledge the following term, which supplements and supersedes any inconsistent provision in the Program Subscription License Agreement connected to this version of the Software:
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Starting with SoCEDS 20.3 Pro and onwards, the components are released to https://github.com/altera-opensource and https://releases.rocketboards.org/. Customers can download exactly what they require, upgraded versions with latest features, bug fixes and security patches. Components are released more frequently enabling faster and better tracking of code changes. Here are the new locations of the SoCEDS components :
1. Golden Hardware Reference Design (GHRD)
https://github.com/altera-opensource/ghrd-socfpga
GHRD is a reference design for Intel System On Chip (SoC) FPGA. The GHRD works together with Golden Software Reference Design (GSRD) for complete solution to boot U-Boot and Linux with an Intel SoC Development board. Note that the GHRD tarball, released as part of the usual Golden System Reference Design (GSRD) releases, are still available at https://releases.rocketboards.org/
For more details, please refer to the README.md file within each GHRD projects
2. Intel SoC FPGA Hardware Library (HWLib)
https://github.com/altera-opensource/intel-socfpga-hwlib
The Intel SoC FPGA Hardware Library (HWLIB) was created to address the needs of low-level software programmers who require full access to the configuration and control facilities of SoC FPGA hardware. Additionally HWLIB is employed to mitigate the complexities of managing the operation of a sophisticated, multi-core application processor and its integration with hardened IP peripheral blocks and programmable logic in a SoC architecture.
For more details, please refer to https://rocketboards.org/foswiki/Documentation/HWLib
3. Boot Tools
https://github.com/altera-opensource/u-boot-socfpga/
As part of the continuous enhancement of tools flow, Arria10 SoC BSP Generator functionality is now merged into U-Boot flow. Arria10 SoC U-Boot is enhanced, where the device tree is now consuming a header file which contains all PLL, clock, pinmux, and bridge configurations information. That header file is now generated by the qts-filter-a10.sh script, directly from the hps_isw_handoff/hps.xml file during the FPGA project compilation.
For more details, please refer to https://rocketboards.org/foswiki/Documentation/BuildingBootloader
Bootloader Image Tool (mkpimage)
https://github.com/altera-opensource/u-boot-socfpga/
The Bootloader Image Tool (mkpimage), which creates an Intel BootROM-compatible image of the Arria V SoC and Cyclone V SoC Preloader or Intel Arria 10 SoC Bootloader, is no longer supported. Instead, it is replaced by the open source version mkimage, which is part of the U-Boot source today. The binary version is available at https://releases.rocketboards.org/, an alternative to the U-Boot source on Github.
4. HPS Flash Programmer
HPS Flash Programmer is part of Quartus Prime Pro Edition Programmer and Tools which can be downloaded from https://fpgasoftware.intel.com/?product=qprogrammer#tabs-4
5. SD card boot utility
This tool is no longer supported as there are off-the-shelf solutions available today such as “dd utility” for Linux operating system or Win32DiskImager